Very Large Scale Integrated (VLSI) chips may contain millions of transistors and electrical connections. Because VLSI chips may be so complex, a great deal of testing may be required to verify that a particular chip is fully functional. Observation of signals internal to modern chip designs can be extremely difficult due to the small size of the features on the chip. Some features on modern chips may be as small as 1 millionth of a meter. These small features can make it very difficult to “probe” an actual electrical node on a VLSI chip. Methods used to probe internal nodes on a VLSI chip include micro probing and e-beam probing. Either of these methods is time consuming and may require various layers of the chip to be physically removed.
Another method used to observe the value or state of an electrical node is to include “scan chain” circuitry along with the normal circuits. A scan chain may include many memory elements that can store electrical values of many nodes of the normal circuitry. These stored values may then be “clocked” from one scan chain memory element to another and then to one or more output pads on a chip. The values presented on the output pads may then be driven to an external tester that may then evaluate the stored electrical values. In order to scan the electrical values captured in the scan chain, the normal operation of the chip must be stopped. Starting and stopping the normal operation of the chip and scanning the state of many electrical nodes may take a great deal of time.
Another method that may be used to test and debug the functionality of a VLSI chip is to use “broadside vectors.” A test program evaluates the function of the VLSI chip and from that evaluation, the program produces a set of signals or “vectors” that may be applied to a VLSI chip. For each set of signals the test program produces to be applied to the VLSI chip, there is another set of signals or vectors that should appear on the outputs of a VLSI chip. An external tester measures the set of outputs that appear on a VLSI chip and determines if these outputs match the values predicted by the test program. By generating many “broadside” vectors, part of the functionality of the VLSI chip may be determined. This method may require a great deal of computer time to create the vectors as well as a great deal of time to actually apply the vectors to the chip.
Scanned vector testing and broadside vector testing both require external test equipment to provide electrical test input to a chip and observe electrical output from a chip. The cost of equipment used to test chips and the cost of facilities to house this equipment can be extremely high. If the amount of external testing required to test a VLSI chip can be reduced, the cost of manufacturing VLSI chips may be reduced.
There is a need in the art to be able to test circuitry on a VLSI chip with a minimal number of external signals. One embodiment of this invention allows the circuitry of I/O (Input/Output) driver/receivers to be tested with very few external signals. This embodiment includes a specific bit pattern generator in the driver section of I/O driver/receiver, which creates a bit pattern that may be recognized by circuitry placed in the receiver section of another I/O driver/receiver, when the I/O driver/receivers are functioning properly. A detailed description of one embodiment of this invention is described later.